Multi-vector floating-point convert from single-precision to packed BFloat16 format
Convert to BFloat16 from single-precision, each element of the two source vectors, and place the results in the half-width destination elements.
This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | Zd | |||||||
| N | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; bits(VL) result; constant bits(VL) operand1 = Z[n+0, VL]; constant bits(VL) operand2 = Z[n+1, VL]; for e = 0 to elements-1 constant bits(32) element1 = Elem[operand1, e, 32]; constant bits(32) element2 = Elem[operand2, e, 32]; constant bits(16) res1 = FPConvertBF(element1, FPCR); constant bits(16) res2 = FPConvertBF(element2, FPCR); Elem[result, e, 16] = res1; Elem[result, elements+e, 16] = res2; Z[d, VL] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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