BFloat16 floating-point fused multiply-subtract vectors
Multiply the corresponding active BFloat16 elements of the first and second source vectors and subtract from elements of the third source (addend) vector without intermediate rounding. Destructively place the results in the destination and third source (addend) vector. Inactive elements in the destination vector register remain unmodified.
This instruction follows SVE2 non-widening BFloat16 numerical behaviors.
ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Zm | 0 | 0 | 1 | Pg | Zn | Zda | ||||||||||||||
| size<1> | size<0> | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE_B16B16) then UNDEFINED; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); constant boolean op1_neg = TRUE; constant boolean op3_neg = FALSE;
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 16; constant bits(PL) mask = P[g, PL]; constant bits(VL) op1 = if AnyActiveElement(mask, 16) then Z[n, VL] else Zeros(VL); constant bits(VL) op2 = if AnyActiveElement(mask, 16) then Z[m, VL] else Zeros(VL); constant bits(VL) op3 = Z[da, VL]; bits(VL) result; for e = 0 to elements-1 if ActivePredicateElement(mask, e, 16) then constant bits(16) elem1 = if op1_neg then BFNeg(Elem[op1, e, 16]) else Elem[op1, e, 16]; constant bits(16) elem2 = Elem[op2, e, 16]; constant bits(16) elem3 = if op3_neg then BFNeg(Elem[op3, e, 16]) else Elem[op3, e, 16]; Elem[result, e, 16] = BFMulAdd(elem3, elem1, elem2, FPCR); else Elem[result, e, 16] = Elem[op3, e, 16]; Z[da, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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