BSL

Bitwise select

Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000100001Zm001111ZkZdn

BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer m = UInt(Zm); constant integer k = UInt(Zk); constant integer dn = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zk>

Is the name of the third source scalable vector register, encoded in the "Zk" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = Z[m, VL]; constant bits(VL) operand3 = Z[k, VL]; Z[dn, VL] = (operand1 AND operand3) OR (operand2 AND NOT(operand3));

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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