CLASTA (SIMD&FP scalar)

Conditionally extract element after last to SIMD&FP scalar register

From the source vector register extract the element after the last active element, or if the last active element is the final element extract element zero, and then zero-extend that element to destructively place in the destination and first source SIMD & floating-point scalar register. If there are no active elements then destructively zero-extend the least significant element-size bits of the destination and first source SIMD & floating-point scalar register.

313029282726252423222120191817161514131211109876543210
00000101size101010100PgZmVdn
B

CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer dn = UInt(Vdn); constant integer m = UInt(Zm); constant boolean isBefore = FALSE;

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size <V>
00 B
01 H
10 S
11 D
<dn>

Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>

Is the name of the source scalable vector register, encoded in the "Zm" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(esize) operand1 = V[dn, esize]; constant bits(VL) operand2 = Z[m, VL]; bits(esize) result; integer last = LastActiveElement(mask, esize); if last < 0 then result = ZeroExtend(operand1, esize); else if !isBefore then last = last + 1; if last >= elements then last = 0; result = Elem[operand2, last, esize]; V[dn, esize] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.