Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | opcode | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CountOp countop = if U == '1' then CountOp_CLZ else CountOp_CLS;
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; integer count; for e = 0 to elements-1 if countop == CountOp_CLS then count = CountLeadingSignBits(Elem[operand, e, esize]); else count = CountLeadingZeroBits(Elem[operand, e, esize]); Elem[result, e, esize] = count<esize-1:0>; V[d, datasize] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.