CMLE (zero)

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
0111111011100000100110RnRd
Usizeop

CMLE D<d>, D<n>, #0

integer d = UInt(Rd); integer n = UInt(Rn); if size != '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = esize; integer elements = 1; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;

Vector

313029282726252423222120191817161514131211109876543210
0Q101110size100000100110RnRd
Uop

CMLE <Vd>.<T>, <Vn>.<T>, #0

integer d = UInt(Rd); integer n = UInt(Rn); if size:Q == '110' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in size:Q:

size Q <T>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 0 RESERVED
11 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones(esize) else Zeros(esize); V[d, datasize] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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