Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This instruction is used by the alias MOV (scalar).
It has encodings from 2 classes: Scalar and Vector
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
op | imm4 |
integer d = UInt(Rd); integer n = UInt(Rn); constant integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>); constant integer esize = 8 << size; constant integer datasize = esize; integer elements = 1;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
op | imm4 |
integer d = UInt(Rd); integer n = UInt(Rn); constant integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>); if size == 3 && Q == '0' then UNDEFINED; constant integer esize = 8 << size; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize;
<V> |
Is the destination width specifier,
encoded in
|
<d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<index> |
Is the element index
encoded in
|
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Ts> |
Is an element size specifier,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n, idxdsize]; bits(datasize) result; bits(esize) element; element = Elem[operand, index, esize]; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d, datasize] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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