DUPM

Broadcast logical bitmask immediate to vector (unpredicated)

Unconditionally broadcast the logical bitmask immediate into each element of the destination vector. This instruction is unpredicated. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits.

This instruction is used by the alias MOV.

313029282726252423222120191817161514131211109876543210
00000101110000imm13Zd

DUPM <Zd>.<T>, #<const>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer d = UInt(Zd); bits(esize) imm; (imm, -) = DecodeBitMasks(imm13<12>, imm13<5:0>, imm13<11:6>, TRUE, esize);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in imm13<12>:imm13<5:0>:

imm13<12> imm13<5:0> <T>
0 0xxxxx S
0 10xxxx H
0 110xxx B
0 1110xx B
0 11110x B
0 111110 RESERVED
0 111111 RESERVED
1 xxxxxx D
<const>

Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

Alias Conditions

AliasIs preferred when
MOVSVEMoveMaskPreferred(imm13)

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) result = Replicate(imm, VL DIV esize); Z[d, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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