F1CVT, F2CVT

Multi-vector floating-point convert from 8-bit floating-point to half-precision (in-order)

Convert each 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the results in the corresponding 16-bit elements of the destination vectors. F1CVT scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVT scales the values by 2-UInt(FPMR.LSCALE2[3:0]). The 8-bit floating-point encoding format for F1CVT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVT is selected by FPMR.F8S2.

This instruction is unpredicated.

It has encodings from 2 classes: F1CVT and F2CVT

F1CVT
(FEAT_FP8)

313029282726252423222120191817161514131211109876543210
1100000100100110111000ZnZd0
L

F1CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B

if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd: '0'); constant boolean issrc2 = FALSE;

F2CVT
(FEAT_FP8)

313029282726252423222120191817161514131211109876543210
1100000110100110111000ZnZd0
L

F2CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B

if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd: '0'); constant boolean issrc2 = TRUE;

Assembler Symbols

<Zd1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckFPMREnabled(); CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 8; constant bits(VL) operand = Z[n, VL]; bits(2*VL) result; for e = 0 to elements-1 constant bits(8) element = Elem[operand, e, 8]; Elem[result, e, 16] = FP8ConvertFP(element, issrc2, FPCR, FPMR); Z[d+0, VL] = result<VL-1:0>; Z[d+1, VL] = result<2*VL-1:VL>;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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