Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar half precision , Scalar single-precision and double-precision , Vector half precision and Vector single-precision and double-precision
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0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
U | a | op |
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = esize; integer elements = 1; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;
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0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | sz | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
U | op |
integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 32 << UInt(sz); constant integer datasize = esize; integer elements = 1; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;
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0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
U | a | op |
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;
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0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | sz | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
U | op |
integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<V> |
Is a width specifier,
encoded in
|
<d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; bits(esize) zero = FPZero('0', esize); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones(esize) else Zeros(esize); V[d, datasize] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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