Multi-vector floating-point convert from single-precision to interleaved 8-bit floating-point format
Convert each single-precision element of the four source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and place the four-way interleaved results in the quarter-width elements of the destination vector. The 8-bit floating-point encoding format is selected by FPMR.F8D.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 1 | Zd | ||||||
| N | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. |
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckFPMREnabled(); CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; bits(VL) result; constant bits(VL) operand1 = Z[n+0, VL]; constant bits(VL) operand2 = Z[n+1, VL]; constant bits(VL) operand3 = Z[n+2, VL]; constant bits(VL) operand4 = Z[n+3, VL]; for e = 0 to elements-1 constant bits(32) element1 = Elem[operand1, e, 32]; constant bits(32) element2 = Elem[operand2, e, 32]; constant bits(32) element3 = Elem[operand3, e, 32]; constant bits(32) element4 = Elem[operand4, e, 32]; Elem[result, 4*e + 0, 8] = FPConvertFP8(element1, FPCR, FPMR, 8); Elem[result, 4*e + 1, 8] = FPConvertFP8(element2, FPCR, FPMR, 8); Elem[result, 4*e + 2, 8] = FPConvertFP8(element3, FPCR, FPMR, 8); Elem[result, 4*e + 3, 8] = FPConvertFP8(element4, FPCR, FPMR, 8); Z[d, VL] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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