Floating-point maximum with immediate (predicated)
Determine the maximum of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate may take the value +0.0 or +1.0 only.
When FPCR.AH is 0, the behavior is as follows:
When FPCR.AH is 1, the behavior is as follows:
Inactive elements in the destination vector register remain unmodified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Pg | 0 | 0 | 0 | 0 | i1 | Zdn |
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant bits(esize) imm = if i1 == '0' then Zeros(esize) else FPOne('0', esize);
<Zdn> |
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
<T> |
Is the size specifier,
encoded in
|
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<const> |
Is the floating-point immediate value,
encoded in
|
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize) element1 = Elem[operand1, e, esize]; if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = FPMax(element1, imm, FPCR); else Elem[result, e, esize] = element1; Z[dn, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.