Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation:
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Half-precision and Single-precision and double-precision
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | a | opcode |
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); constant integer esize = 16; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean pair = (U == '1'); boolean minimum = (a == '1');
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 0 | sz | 1 | Rm | 1 | 1 | 0 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | o1 | opcode |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sz:Q == '10' then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean pair = (U == '1'); boolean minimum = (o1 == '1');
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d, datasize] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.