FMAXV

Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

When FPCR.AH is 0, the behavior is as follows:

When FPCR.AH is 1, the behavior is as follows:

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Half-precision and Single-precision

Half-precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0Q00111000110000111110RnRd
Uo1opcode

FMAXV <V><d>, <Vn>.<T>

if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = 64 << UInt(Q);

Single-precision

313029282726252423222120191817161514131211109876543210
0110111000110000111110RnRd
QUo1szopcode

FMAXV S<d>, <Vn>.4S

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q != '01' then UNDEFINED; constant integer esize = 32; constant integer datasize = 64 << UInt(Q);

Assembler Symbols

<V>

Is the destination width specifier, H.

<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<T>

Is an arrangement specifier, encoded in Q:

Q <T>
0 4H
1 8H

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; V[d, esize] = FPReduce(ReduceOp_FMAX, operand, esize, FPCR);


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.