FMINP (scalar)

Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.

When FPCR.AH is 0, the behavior is as follows for each pairwise operation:

When FPCR.AH is 1, the behavior is as follows for each pairwise operation:

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Half-precision and Single-precision and double-precision

Half-precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0101111010110000111110RnRd
Uo1szopcode

FMINP H<d>, <Vn>.2H

if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; if sz == '1' then UNDEFINED; constant integer datasize = 32;

Single-precision and double-precision

313029282726252423222120191817161514131211109876543210
011111101sz110000111110RnRd
Uo1opcode

FMINP <V><d>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 32 << UInt(sz); constant integer datasize = esize * 2;

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<V>

Is the destination width specifier, encoded in sz:

sz <V>
0 S
1 D
<T>

Is the source arrangement specifier, encoded in sz:

sz <T>
0 2S
1 2D

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; V[d, esize] = FPReduce(ReduceOp_FMIN, operand, esize, FPCR);


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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