FMINQV

Floating-point minimum recursive reduction of quadword vector segments

Floating-point minimum of the same element numbers from each 128-bit source vector segment using a recursive pairwise reduction, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as +Infinity.

When FPCR.AH is 0, the behavior is as follows:

When FPCR.AH is 1, the behavior is as follows:

SVE2
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
01100100size010111101PgZnVd

FMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Vd);

Assembler Symbols

<Vd>

Is the name of the destination SIMD&FP register, encoded in the "Vd" field.

<T>

Is an arrangement specifier, encoded in size:

size <T>
00 RESERVED
01 8H
10 4S
11 2D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size <Tb>
00 RESERVED
01 H
10 S
11 D

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer segments = VL DIV 128; constant integer elempersegment = 128 DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); constant bits(esize) identity = FPInfinity('0', esize); bits(128) result = Zeros(128); constant integer p2bits = CeilPow2(segments*esize); constant integer p2elems = p2bits DIV esize; for e = 0 to elempersegment-1 bits(p2bits) stmp; bits(esize) dtmp; for s = 0 to p2elems-1 if s < segments && ActivePredicateElement(mask, s * elempersegment + e, esize) then Elem[stmp, s, esize] = Elem[operand, s * elempersegment + e, esize]; else Elem[stmp, s, esize] = identity; dtmp = FPReduce(ReduceOp_FMIN, stmp, esize, FPCR); Elem[result, e, esize] = dtmp; V[d, 128] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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