Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar, half-precision , Scalar, single-precision and double-precision , Vector, half-precision and Vector, single-precision and double-precision
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0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U | size | opcode |
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant integer idxdsize = 64 << UInt(H); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer index = UInt(H:L:M); constant integer esize = 16; constant integer datasize = esize; integer elements = 1; boolean mulx_op = (U == '1');
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0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U | opcode |
constant integer idxdsize = 64 << UInt(H); integer index; bit Rmhi = M; case sz:L of when '0x' index = UInt(H:L); when '10' index = UInt(H); when '11' UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); constant integer esize = 32 << UInt(sz); constant integer datasize = esize; integer elements = 1; boolean mulx_op = (U == '1');
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0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U | size | opcode |
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant integer idxdsize = 64 << UInt(H); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer index = UInt(H:L:M); constant integer esize = 16; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean mulx_op = (U == '1');
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0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U | opcode |
constant integer idxdsize = 64 << UInt(H); integer index; bit Rmhi = M; case sz:L of when '0x' index = UInt(H:L); when '10' index = UInt(H); when '11' UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); if sz:Q == '10' then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean mulx_op = (U == '1');
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<V> |
Is a width specifier,
encoded in
|
<d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<Ts> |
Is an element size specifier,
encoded in
|
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
For the half-precision variant: is an arrangement specifier,
encoded in
| |||||||||||||||
For the single-precision and double-precision variant: is an arrangement specifier,
encoded in
|
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(idxdsize) operand2 = V[m, idxdsize]; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; boolean merge = elements == 1 && IsMerging(FPCR); bits(128) result = if merge then V[n, 128] else Zeros(128); for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d, 128] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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