Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: No offset and Post-index
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | x | x | 0 | S | size | Rn | Rt | |||||||||
| L | R | o2 | opcode | ||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn); integer m = integer UNKNOWN; boolean wback = FALSE; boolean nontemporal = FALSE; boolean tagchecked = wback || n != 31;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | Rm | x | x | 0 | S | size | Rn | Rt | |||||||||||||
| L | R | opcode | |||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn); integer m = UInt(Rm); boolean wback = TRUE; boolean nontemporal = FALSE; boolean tagchecked = wback || n != 31;
| <Vt> |
Is the name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field. |
bits(2) scale = opcode<2:1>; integer selem = UInt(opcode<0>:R) + 1; boolean replicate = FALSE; integer index; case scale of when '11' // load and replicate if L == '0' || S == '1' then UNDEFINED; scale = size; replicate = TRUE; when '00' index = UInt(Q:S:size); // B[0-15] when '01' if size<0> == '1' then UNDEFINED; index = UInt(Q:S:size<1>); // H[0-7] when '10' if size<1> == '1' then UNDEFINED; if size<0> == '0' then index = UInt(Q:S); // S[0-3] else if S == '1' then UNDEFINED; index = UInt(Q); // D[0-1] scale = '11'; constant integer datasize = 64 << UInt(Q); constant integer esize = 8 << UInt(scale);
CheckFPAdvSIMDEnabled64(); bits(64) address; bits(64) eaddr; bits(64) offs; bits(128) rval; bits(esize) element; constant integer ebytes = esize DIV 8; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; offs = Zeros(64); if replicate then // load and replicate to all elements for s = 0 to selem-1 eaddr = AddressIncrement(address, offs, accdesc); element = Mem[eaddr, ebytes, accdesc]; // replicate to fill 128- or 64-bit register V[t, datasize] = Replicate(element, datasize DIV esize); offs = offs + ebytes; t = (t + 1) MOD 32; else // load/store one element per register for s = 0 to selem-1 rval = V[t, 128]; eaddr = AddressIncrement(address, offs, accdesc); Elem[rval, index, esize] = Mem[eaddr, ebytes, accdesc]; V[t, 128] = rval; offs = offs + ebytes; t = ( t + 1 ) MOD 32; if wback then if m != 31 then offs = X[m, 64]; address = AddressAdd(address, offs, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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