Gather load unsigned halfwords to vector (immediate index)
Gather load of unsigned halfwords to active elements of a vector register from memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 2 classes: 32-bit element and 64-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt | ||||||||||||||
| msz<1> | msz<0> | U | ff | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = UInt(imm5);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt | ||||||||||||||
| msz<1> | msz<0> | U | ff | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = UInt(imm5);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field. |
CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(VL) base; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, esize) then base = Z[n, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(64) baddr = ZeroExtend(Elem[base, e, esize], 64); constant bits(64) addr = AddressAdd(baddr, offset * mbytes, accdesc); data = Mem[addr, mbytes, accdesc]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(esize); Z[t, VL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.