LD1RB

Load and broadcast unsigned byte to vector

Load a single unsigned byte from a memory address generated by a 64-bit scalar base address plus an immediate offset which is in the range 0 to 63.

Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.

It has encodings from 4 classes: 8-bit element , 16-bit element , 32-bit element and 64-bit element

8-bit element

313029282726252423222120191817161514131211109876543210
1000010001imm6100PgRnZt
dtypeh<1>dtypeh<0>dtypel<1>dtypel<0>

LD1RB { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 8; constant integer msize = 8; constant boolean unsigned = TRUE; constant integer offset = UInt(imm6);

16-bit element

313029282726252423222120191817161514131211109876543210
1000010001imm6101PgRnZt
dtypeh<1>dtypeh<0>dtypel<1>dtypel<0>

LD1RB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 16; constant integer msize = 8; constant boolean unsigned = TRUE; constant integer offset = UInt(imm6);

32-bit element

313029282726252423222120191817161514131211109876543210
1000010001imm6110PgRnZt
dtypeh<1>dtypeh<0>dtypel<1>dtypel<0>

LD1RB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 8; constant boolean unsigned = TRUE; constant integer offset = UInt(imm6);

64-bit element

313029282726252423222120191817161514131211109876543210
1000010001imm6111PgRnZt
dtypeh<1>dtypeh<0>dtypel<1>dtypel<0>

LD1RB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 8; constant boolean unsigned = TRUE; constant integer offset = UInt(imm6);

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional unsigned immediate byte offset, in the range 0 to 63, defaulting to 0, encoded in the "imm6" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; constant bits(64) addr = AddressAdd(base, offset * mbytes, accdesc); data = Mem[addr, mbytes, accdesc]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(esize); Z[t, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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