LDAPR

Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

• There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction.
• The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.

This difference in memory ordering is not described in the pseudocode.

For information about addressing modes, see Load/Store addressing modes.

It has encodings from 2 classes: Post-index and No offset

Post-index
(FEAT_LRCPC3)

integer t = UInt(Rt); integer n = UInt(Rn); boolean wback = TRUE; constant integer regsize = if size == '11' then 64 else 32; constant integer datasize = 8 << UInt(size); constant integer offset = 1 << UInt(size); boolean tagchecked = TRUE; boolean wb_unknown = FALSE; if n == t && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

No offset
(FEAT_LRCPC)

if !IsFeatureImplemented(FEAT_LRCPC) then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); boolean wback = FALSE; integer offset = 0; boolean wb_unknown = FALSE; constant integer elsize = 8 << UInt(size); constant integer regsize = if elsize == 64 then 64 else 32; constant integer datasize = elsize; boolean tagchecked = n != 31;