LDAPR

Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

This difference in memory ordering is not described in the pseudocode.

For information about addressing modes, see Load/Store addressing modes.

It has encodings from 2 classes: Post-index and No offset

Post-index
(FEAT_LRCPC3)

313029282726252423222120191817161514131211109876543210
1x01100111000000000010RnRt
sizeL

32-bit (size == 10)

LDAPR <Wt>, [<Xn|SP>], #4

64-bit (size == 11)

LDAPR <Xt>, [<Xn|SP>], #8

integer t = UInt(Rt); integer n = UInt(Rn); boolean wback = TRUE; constant integer regsize = if size == '11' then 64 else 32; constant integer datasize = 8 << UInt(size); constant integer offset = 1 << UInt(size); boolean tagchecked = TRUE; boolean wb_unknown = FALSE; if n == t && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

No offset
(FEAT_LRCPC)

313029282726252423222120191817161514131211109876543210
1x111000101(1)(1)(1)(1)(1)110000RnRt
sizeVRARRso3opc

32-bit (size == 10)

LDAPR <Wt>, [<Xn|SP> {, #0}]

64-bit (size == 11)

LDAPR <Xt>, [<Xn|SP> {, #0}]

if !IsFeatureImplemented(FEAT_LRCPC) then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); boolean wback = FALSE; integer offset = 0; boolean wb_unknown = FALSE; constant integer elsize = 8 << UInt(size); constant integer regsize = if elsize == 64 then 64 else 32; constant integer datasize = elsize; boolean tagchecked = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

Operation

bits(64) address; bits(datasize) data; constant integer dbytes = datasize DIV 8; AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = Mem[address, dbytes, accdesc]; X[t, regsize] = ZeroExtend(data, regsize); if wback then if wb_unknown then address = bits(64) UNKNOWN; else address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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