LDAPURSH

Load-Acquire RCpc Register Signed Halfword (unscaled) calculates an address from a base register and an immediate offset, loads a signed halfword from memory, sign-extends it, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

This difference in memory ordering is not described in the pseudocode.

For information about addressing modes, see Load/Store addressing modes.

Unscaled offset
(FEAT_LRCPC2)

313029282726252423222120191817161514131211109876543210
010110011x0imm900RnRt
sizeopc

32-bit (opc == 11)

LDAPURSH <Wt>, [<Xn|SP>{, #<simm>}]

64-bit (opc == 10)

LDAPURSH <Xt>, [<Xn|SP>{, #<simm>}]

if !IsFeatureImplemented(FEAT_LRCPC2) then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

Shared Decode

integer t = UInt(Rt); integer n = UInt(Rn); integer regsize = 64 >> UInt(opc<0>); boolean tagchecked = n != 31;

Operation

bits(64) address; AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); bits(16) data = Mem[address, 2, accdesc]; X[t, regsize] = SignExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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