LDLAR

Load LOAcquire Register loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.


Note

For this instruction, if the destination is WZR/XZR, it is impossible for software to observe the presence of the acquire semantic other than its effect on the arrival at endpoints.


No offset
(FEAT_LOR)

313029282726252423222120191817161514131211109876543210
1x001000110(1)(1)(1)(1)(1)0(1)(1)(1)(1)(1)RnRt
sizeLRso0Rt2

32-bit (size == 10)

LDLAR <Wt>, [<Xn|SP>{, #0}]

64-bit (size == 11)

LDLAR <Xt>, [<Xn|SP>{, #0}]

if !IsFeatureImplemented(FEAT_LOR) then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); constant integer elsize = 8 << UInt(size); constant integer regsize = if elsize == 64 then 64 else 32; boolean tagchecked = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

Operation

bits(64) address; constant integer dbytes = elsize DIV 8; AccessDescriptor accdesc = CreateAccDescLOR(MemOp_LOAD, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; bits(elsize) data = Mem[address, dbytes, accdesc]; X[t, regsize] = ZeroExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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