LDR (register)

Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted and extended. For information about addressing modes, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
1x111000011RmoptionS10RnRt
sizeVRopc

32-bit (size == 10)

LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]

64-bit (size == 11)

LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]

if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer scale = UInt(size); integer shift = if S == '1' then scale else 0;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Wm>

When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm>

When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

<extend>

Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted. encoded in option:

option <extend>
010 UXTW
011 LSL
110 SXTW
111 SXTX
<amount>

For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S <amount>
0 #0
1 #2

For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S <amount>
0 #0
1 #3
<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

Shared Decode

integer t = UInt(Rt); integer n = UInt(Rn); integer m = UInt(Rm); constant integer datasize = 8 << scale; integer regsize = if datasize == 64 then 64 else 32; boolean nontemporal = FALSE; boolean tagchecked = TRUE;

Operation

bits(64) offset = ExtendReg(m, extend_type, shift, 64); bits(64) address; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); bits(datasize) data = Mem[address, datasize DIV 8, accdesc]; X[t, regsize] = ZeroExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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