Atomic bit set on quadword in memory atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and stores the result back to memory. The value initially loaded from memory is returned in the same pair of registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | A | R | 1 | Rt2 | 0 | 0 | 1 | 1 | 0 | 0 | Rn | Rt | ||||||||||||
| S | o3 | opc | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSE128) then UNDEFINED; if Rt == '11111' then UNDEFINED; if Rt2 == '11111' then UNDEFINED; integer t = UInt(Rt); integer t2 = UInt(Rt2); integer n = UInt(Rn); boolean acquire = A == '1'; boolean release = R == '1'; boolean tagchecked = n != 31; boolean rt_unknown = FALSE; if t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LSE128OVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly CONSTRAINED UNPREDICTABLE behavior for A64 instructions.
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(64) value1 = X[t, 64]; bits(64) value2 = X[t2, 64]; bits(128) data; bits(128) store_value; AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_ORR, acquire, release, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; store_value = if BigEndian(accdesc.acctype) then value1:value2 else value2:value1; bits(128) comparevalue = bits(128) UNKNOWN; // Irrelevant when not executing CAS data = MemAtomic(address, comparevalue, store_value, accdesc); if rt_unknown then data = bits(128) UNKNOWN; if BigEndian(accdesc.acctype) then X[t, 64] = data<127:64>; X[t2, 64] = data<63:0>; else X[t, 64] = data<63:0>; X[t2, 64] = data<127:64>;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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