Lookup table read with 4-bit indices. This instruction copies indexed 8-bit or 16-bit elements from the one or two table vectors to the destination vector using packed 4-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | len | op | 0 | 0 | Rn | Rd | |||||||||||||
| Q | op2 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LUT) then UNDEFINED; if len<0> == '0' && op == '0' then UNDEFINED; constant integer isize = 4; constant integer esize = 8 << UInt(op); integer ntblr = 1 << UInt(op); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer part = if op == '0' then UInt(len<1>) else UInt(len);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the SIMD&FP table register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the SIMD&FP source register, encoded in the "Rm" field. |
| <Vn1> |
Is the name of the first SIMD&FP table register, encoded in the "Rn" field. |
| <Vn2> |
Is the name of the second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32. |
CheckFPAdvSIMDEnabled64(); integer elements = 128 DIV esize; integer ibase = elements * part; bits(128) indices = V[m, 128]; bits(128) table1 = V[n+0, 128]; bits(128) table2 = if ntblr == 2 then V[(n+1) MOD 32, 128] else Zeros(128); bits(128) result; bits(esize) res; for e = 0 to elements-1 integer index = UInt(Elem[indices, ibase+e, isize]); if index < elements then res = Elem[table1, index, esize]; else assert ntblr == 2; res = Elem[table2, index-elements, esize]; Elem[result, e, esize] = res; V[d, 128] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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