LUTI4 (four registers, 16-bit & 32-bit)

Copy 16-bit or 32-bit elements from ZT0 to four destination vectors using packed 4-bit indices from a segment of the source vector register. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index modulo the total number of segments.

Consecutive
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if size == '00' || size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer isize = 4; constant integer n = UInt(Zn); constant integer dstride = 1; constant integer d = UInt(Zd:'00'); constant integer imm = UInt(i1); constant integer nreg = 4;

Strided
(FEAT_SME2p1)

if !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; if size != '01' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer isize = 4; constant integer n = UInt(Zn); constant integer dstride = 4; constant integer d = UInt(D:'00':Zd); constant integer imm = UInt(i1); constant integer nreg = 4;

Assembler Symbols

<Zd1>	For the consecutive variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.
	For the strided variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	RESERVED

<Zd4>	For the consecutive variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.
	For the strided variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<index>

Is the vector segment index, in the range 0 to 1, encoded in the "i1" field.

Operation

CheckStreamingSVEEnabled(); CheckSMEZT0Enabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer segments = esize DIV (isize * nreg); constant integer segment = imm MOD segments; constant bits(VL) indexes = Z[n, VL]; integer dst = d; constant bits(512) table = ZT0[512]; for r = 0 to nreg-1 constant integer base = (segment * nreg + r) * elements; bits(VL) result; for e = 0 to elements-1 constant integer index = UInt(Elem[indexes, base+e, isize]); Elem[result, e, esize] = Elem[table, index, 32]<esize-1:0>; Z[dst, VL] = result; dst = dst + dstride;

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45