Lookup table read with 4-bit indices
This instruction copies indexed 8-bit or 16-bit elements from the low 128 or 256 bits of the table vector, or from the low 128 bits of the two table vectors to the destination vector using packed 4-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index. This instruction is unpredicated.
It has encodings from 3 classes: Byte, single register table , Halfword, two register table and Halfword, single register table
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | i1 | 1 | 1 | Zm | 1 | 0 | 1 | 0 | 0 | 1 | Zn | Zd | ||||||||||||
if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_LUT)) then UNDEFINED; constant integer isize = 4; constant integer esize = 8; constant integer ntblr = 1; constant integer m = UInt(Zm); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer part = UInt(i1);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | i2 | 1 | Zm | 1 | 0 | 1 | 1 | 0 | 1 | Zn | Zd | |||||||||||||
if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_LUT)) then UNDEFINED; constant integer isize = 4; constant integer esize = 16; constant integer ntblr = 2; constant integer m = UInt(Zm); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer part = UInt(i2);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | i2 | 1 | Zm | 1 | 0 | 1 | 1 | 1 | 1 | Zn | Zd | |||||||||||||
if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_LUT)) then UNDEFINED; if MaxImplementedAnyVL() < 256 then UNDEFINED; constant integer isize = 4; constant integer esize = 16; constant integer ntblr = 1; constant integer m = UInt(Zm); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer part = UInt(i2);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn> |
Is the name of the table vector register, encoded in the "Zn" field. |
| <Zn1> |
Is the name of the first table vector register, encoded as "Zn". |
| <Zn2> |
Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32. |
| <Zm> |
Is the name of the source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; if ntblr == 1 && esize == 16 && VL < 256 then UNDEFINED; constant integer elements = VL DIV esize; constant integer tablesize = if ntblr == 1 && esize == 16 then 256 else 128; constant integer eltspertable = tablesize DIV esize; constant integer ibase = elements * part; constant bits(VL) indices = Z[m, VL]; constant bits(VL) table1 = Z[n+0, VL]; constant bits(VL) table2 = if ntblr == 2 then Z[(n+1) MOD 32, VL] else Zeros(VL); bits(VL) result; bits(esize) res; for e = 0 to elements-1 constant integer index = UInt(Elem[indices, ibase + e, isize]); if index < eltspertable then res = Elem[table1, index, esize]; else assert ntblr == 2; res = Elem[table2, index - eltspertable, esize]; Elem[result, e, esize] = res; Z[d, VL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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