Multiply-add checked pointer vectors, writing addend [Zda = Zda + Zn * Zm]
Multiply with overflow check the elements of the first and second source vectors and add pointer check to elements of the third source (addend) vector. Destructively place the results in the destination and third source (addend) vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | Zm | 1 | 1 | 0 | 1 | 0 | 0 | Zn | Zda | ||||||||||||
if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_CPA) then UNDEFINED; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda);
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 64; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; constant bits(VL) operand3 = Z[da, VL]; bits(VL) result; for e = 0 to elements-1 constant integer element1 = SInt(Elem[operand1, e, 64]); constant integer element2 = SInt(Elem[operand2, e, 64]); constant integer product = element1 * element2; constant boolean overflow = (product != SInt(product<63:0>)); constant bits(64) addend = Elem[operand3, e, 64]; Elem[result, e, 64] = PointerMultiplyAddCheck(addend + product, addend, overflow); Z[da, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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