MOVN -- A64

Move wide with NOT moves the inverse of an optionally-shifted 16-bit immediate value to a register.

if sf == '0' && hw<1> == '1' then UNDEFINED; integer d = UInt(Rd); constant integer datasize = 32 << UInt(sf); constant bits(16) imm = imm16; constant integer pos = UInt(hw:'0000');

Assembler Symbols

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<imm>

Is the 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

<shift>	For the 32-bit variant: is the amount by which to shift the immediate left, either 0 (the default) or 16, encoded in the "hw" field as <shift>/16.
	For the 64-bit variant: is the amount by which to shift the immediate left, either 0 (the default), 16, 32 or 48, encoded in the "hw" field as <shift>/16.

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

Alias Conditions

Alias	Of variant	Is preferred when
MOV (inverted wide immediate)	32-bit	!(IsZero(imm16) && hw != '00') && !IsOnes(imm16)
MOV (inverted wide immediate)	64-bit	!(IsZero(imm16) && hw != '00')

Operation

bits(datasize) result = Zeros(datasize); result<pos+15:pos> = imm; X[d, datasize] = NOT(result);

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
sf	0	0	1	0	0	1	0	1	hw		imm16																Rd
	opc

MOVN

32-bit (sf == 0 && hw == 0x)

64-bit (sf == 1)

Assembler Symbols

Alias Conditions

Operation

Operational information