Move predicate to vector
Copy the source SVE predicate register elements into the destination vector register as a packed bitmap with one bit per predicate element, where bit value 0b1 represents a TRUE predicate element, and bit value 0b0 represents a FALSE predicate element.
Because the number of bits in an SVE predicate element scales with the the vector element size, the behavior varies according to the specified element size.
The portion index is optional, defaulting to 0 if omitted. When the index is zero, the instruction writes zeroes to the most significant VL-(VL/esize) bits of the destination vector register. When a non-zero index is specified, the packed bitmap is inserted into the destination vector register, and the unindexed blocks remain unchanged.
It has encodings from 4 classes: Byte , Doubleword , Halfword and Word
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0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Pn | Zd |
if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 8; constant integer imm = 0;
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0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | i3h | 1 | 0 | 1 | i3l | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Pn | Zd |
if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 64; constant integer imm = UInt(i3h:i3l);
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0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | i1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Pn | Zd |
if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 16; constant integer imm = UInt(i1);
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0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | i2 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Pn | Zd |
if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 32; constant integer imm = UInt(i2);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<Pn> |
Is the name of the source scalable predicate register, encoded in the "Pn" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) operand = P[n, PL]; bits(VL) result; if imm == 0 then result = Zeros(VL); else result = Z[d, VL]; for e = 0 to elements-1 result<(elements * imm) + e> = PredicateElement(operand, e, esize); Z[d, VL] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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