PMOV (to vector)

Move predicate to vector

Copy the source SVE predicate register elements into the destination vector register as a packed bitmap with one bit per predicate element, where bit value 0b1 represents a TRUE predicate element, and bit value 0b0 represents a FALSE predicate element.

Because the number of bits in an SVE predicate element scales with the the vector element size, the behavior varies according to the specified element size.

The portion index is optional, defaulting to 0 if omitted. When the index is zero, the instruction writes zeroes to the most significant VL-(VL/esize) bits of the destination vector register. When a non-zero index is specified, the packed bitmap is inserted into the destination vector register, and the unindexed blocks remain unchanged.

It has encodings from 4 classes: Byte , Doubleword , Halfword and Word

Byte
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
00000101001010110011100PnZd

PMOV <Zd>, <Pn>.B

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 8; constant integer imm = 0;

Doubleword
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
000001011i3h101i3l10011100PnZd

PMOV <Zd>{[<imm>]}, <Pn>.D

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 64; constant integer imm = UInt(i3h:i3l);

Halfword
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
00000101001011i110011100PnZd

PMOV <Zd>{[<imm>]}, <Pn>.H

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 16; constant integer imm = UInt(i1);

Word
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
0000010101101i210011100PnZd

PMOV <Zd>{[<imm>]}, <Pn>.S

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer n = UInt(Pn); constant integer d = UInt(Zd); constant integer esize = 32; constant integer imm = UInt(i2);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<imm>

For the doubleword variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields.

For the halfword variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field.

For the word variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field.

<Pn>

Is the name of the source scalable predicate register, encoded in the "Pn" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) operand = P[n, PL]; bits(VL) result; if imm == 0 then result = Zeros(VL); else result = Z[d, VL]; for e = 0 to elements-1 result<(elements * imm) + e> = PredicateElement(operand, e, esize); Z[d, VL] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.