PMULLB

Polynomial multiply long (bottom)

Polynomial multiply over [0, 1] the corresponding even-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.

ID_AA64ZFR0_EL1.AES indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 2 classes: 16-bit or 64-bit elements and 128-bit element

16-bit or 64-bit elements

313029282726252423222120191817161514131211109876543210
01000101!= 000Zm011010ZnZd
sizeUT

PMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size<0> == '0' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd);

128-bit element
(FEAT_SVE_PMULL128)

313029282726252423222120191817161514131211109876543210
01000101000Zm011010ZnZd
size<1>size<0>UT

PMULLB <Zd>.Q, <Zn>.D, <Zm>.D

if !IsFeatureImplemented(FEAT_SVE_PMULL128) then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size<1>:

size<1> <T>
0 H
1 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size<1>:

size<1> <Tb>
0 B
1 S
<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize DIV 2) element1 = Elem[operand1, 2*e + 0, esize DIV 2]; constant bits(esize DIV 2) element2 = Elem[operand2, 2*e + 0, esize DIV 2]; Elem[result, e, esize] = PolynomialMult(element1, element2); Z[d, VL] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.