Return predicate of succesfully loaded elements, setting the condition flags
Read the first-fault register (FFR) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Pg | 0 | Pd | ||||||
| S | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer g = UInt(Pg); constant integer d = UInt(Pd); constant boolean setflags = TRUE;
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant bits(PL) mask = P[g, PL]; constant bits(PL) ffr = FFR[PL]; constant bits(PL) result = ffr AND mask; if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, 8); P[d, PL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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