SHA1P

SHA1 hash update (parity).

Advanced SIMD
(FEAT_SHA1)

313029282726252423222120191817161514131211109876543210
01011110000Rm000100RnRd
sizeopcode

SHA1P <Qd>, <Sn>, <Vm>.4S

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !IsFeatureImplemented(FEAT_SHA1) then UNDEFINED;

Assembler Symbols

<Qd>

Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) x = V[d, 128]; bits(32) y = V[n, 32]; // Note: 32 not 128 bits wide bits(128) w = V[m, 128]; bits(32) t; for e = 0 to 3 t = SHAparity(x<63:32>, x<95:64>, x<127:96>); y = y + ROL(x<31:0>, 5) + t + Elem[w, e, 32]; x<63:32> = ROL(x<63:32>, 30); <y, x> = ROL(y:x, 32); V[d, 128] = x;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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