SHA256H2 -- A64

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !IsFeatureImplemented(FEAT_SHA256) then UNDEFINED;

<Qd>	Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.

<Qn>	Is the 128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>	Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

AArch64.CheckFPAdvSIMDEnabled(); bits(128) result; result = SHA256hash(V[n, 128], V[d, 128], V[m, 128], FALSE); V[d, 128] = result;

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

SHA256H2