SHA256SU0

SHA256 schedule update 0.

Advanced SIMD
(FEAT_SHA256)

313029282726252423222120191817161514131211109876543210
0101111000101000001010RnRd
sizeopcode

SHA256SU0 <Vd>.4S, <Vn>.4S

integer d = UInt(Rd); integer n = UInt(Rn); if !IsFeatureImplemented(FEAT_SHA256) then UNDEFINED;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) operand1 = V[d, 128]; bits(128) operand2 = V[n, 128]; bits(128) result; bits(128) T = operand2<31:0>:operand1<127:32>; bits(32) elt; for e = 0 to 3 elt = Elem[T, e, 32]; elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3); Elem[result, e, 32] = elt + Elem[operand1, e, 32]; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.