SHA256SU1

SHA256 schedule update 1.

Advanced SIMD
(FEAT_SHA256)

313029282726252423222120191817161514131211109876543210
01011110000Rm011000RnRd
sizeopcode

SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !IsFeatureImplemented(FEAT_SHA256) then UNDEFINED;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) operand1 = V[d, 128]; bits(128) operand2 = V[n, 128]; bits(128) operand3 = V[m, 128]; bits(128) result; bits(128) T0 = operand3<31:0>:operand2<127:32>; bits(64) T1; bits(32) elt; T1 = operand3<127:64>; for e = 0 to 1 elt = Elem[T1, e, 32]; elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10); elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32]; Elem[result, e, 32] = elt; T1 = result<63:0>; for e = 2 to 3 elt = Elem[T1, e-2, 32]; elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10); elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32]; Elem[result, e, 32] = elt; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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