SHA512 Schedule Update 0 takes the values from the two 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the gamma0 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||
| opcode | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SHA512) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn);
| <Vd> |
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(64) sig0; bits(128) Vtmp; bits(128) x = V[n, 128]; bits(128) w = V[d, 128]; sig0 = ROR(w<127:64>, 1) EOR ROR(w<127:64>, 8) EOR ('0000000':w<127:71>); Vtmp<63:0> = w<63:0> + sig0; sig0 = ROR(x<63:0>, 1) EOR ROR(x<63:0>, 8) EOR ('0000000':x<63:7>); Vtmp<127:64> = w<127:64> + sig0; V[d, 128] = Vtmp;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.