SME load array vector (elements)<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME load array vector (quadwords)<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME move array to vector<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME move vector to array<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME store array vector (elements)<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME store array vector (quadwords)<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME zeroing move array to vector<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME2 lookup table expand four contiguous registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SME2 lookup table expand four contiguous registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->RESERVED.

SME2 lookup table expand four non-contiguous registers<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.

SME2 lookup table expand one register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SME2 lookup table expand two contiguous registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SME2 lookup table expand two non-contiguous registers<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.

SME2 move tile to vector, four registers<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME2 move tile to vector, two registers<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME2 move vector to tile, four registers<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME2 move vector to tile, two registers<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME2 multi-vec CLAMP four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vec CLAMP two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vec FCLAMP four registers<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SME2 multi-vec FCLAMP two registers<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SME2 multi-vec ZIP four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vec ZIP two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vec int down convert four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 multi-vec int down convert four registers<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multi-vec saturating shift right narrow four registers<T>

Original text: Is the size specifier, encoded in "tsize", where 00->RESERVED, 01->B and 1x->H.

SME2 multi-vec saturating shift right narrow four registers<Tb>

Original text: Is the size specifier, encoded in "tsize", where 00->RESERVED, 01->S and 1x->D.

SME2 multi-vec select four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vec select two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vec unpack four registers<Tb>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.

SME2 multi-vec unpack four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multi-vec unpack two registers<Tb>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.

SME2 multi-vec unpack two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multi-vector signed saturating doubling multiply high four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multi-vector signed saturating doubling multiply high two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multiple and single vector FSCALE four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multiple and single vector FSCALE two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multiple and single vector long long FMA one source<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 multiple and single vector long long FMA one source<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors FP min/max four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multiple vectors FP min/max four registers<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SME2 multiple vectors FP min/max two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multiple vectors FP min/max two registers<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SME2 multiple vectors FSCALE four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multiple vectors FSCALE two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SME2 multiple vectors binary FP four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors binary FP two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors binary int four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors binary int two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors four-way dot product four registers<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 multiple vectors four-way dot product four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors four-way dot product two registers<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 multiple vectors four-way dot product two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors int min/max four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multiple vectors int min/max two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multiple vectors long long MLA four sources<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 multiple vectors long long MLA four sources<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors long long MLA two sources<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 multiple vectors long long MLA two sources<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors shift four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multiple vectors shift two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 multiple vectors ternary FP four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors ternary FP two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors ternary int four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 multiple vectors ternary int two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi FP min/max four registers<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SME2 single-multi FP min/max two registers<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SME2 single-multi add four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi add two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi four-way dot product four registers<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 single-multi four-way dot product four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi four-way dot product two registers<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 single-multi four-way dot product two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi int min/max four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi int min/max two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi long long MLA four sources<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 single-multi long long MLA four sources<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi long long MLA two sources<Tb>

Original text: Is the size specifier, encoded in "sz", where 0->B and 1->H.

SME2 single-multi long long MLA two sources<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi shift four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi shift two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi signed saturating doubling multiply high four registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi signed saturating doubling multiply high two registers<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SME2 single-multi ternary FP four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi ternary FP two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi ternary int four registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 single-multi ternary int two registers<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SME2 zeroing move tile to vector, four registers<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SME2 zeroing move tile to vector, two registers<HV>

Original text: Is the horizontal or vertical slice indicator, encoded in the "V" field, where 0->H and 1->V.

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE 32-bit gather prefetch (vector plus immediate)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE 64-bit gather prefetch (vector plus immediate)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

SVE FP clamp<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SVE address generation<mod>

Original text: Is the index extend and shift specifier, encoded in "msz", where 00->[absent], 10->LSL and x1->LSL.

SVE address generation<amount>

Original text: Is the index shift amount, encoded in "msz", where 00->[absent], 01->#1, 10->#2 and 11->#3.

SVE address generation<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SVE bitwise logical operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE bitwise logical reduction (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE bitwise logical reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE bitwise logical reduction (quadwords)<T>

Original text: Is an arrangement specifier, encoded in "size", where 00->16B, 01->8H, 10->4S and 11->2D.

SVE bitwise logical reduction (quadwords)<Tb>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE bitwise logical with immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "imm13<12>:imm13<5:0>", where 0111111->RESERVED, 0111110->RESERVED, 011110x->B, 01110xx->B, 0110xxx->B, 010xxxx->H, 00xxxxx->S and 1xxxxxx->D.

SVE bitwise shift by immediate (predicated)<T>

Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.

SVE bitwise shift by immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.

SVE bitwise shift by vector (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE bitwise shift by wide elements (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SVE bitwise shift by wide elements (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SVE bitwise unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE bitwise unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE broadcast bitmask immediate<T>

Original text: Is the size specifier, encoded in "imm13<12>:imm13<5:0>", where 0111111->RESERVED, 0111110->RESERVED, 011110x->B, 01110xx->B, 0110xxx->B, 010xxxx->H, 00xxxxx->S and 1xxxxxx->D.

SVE broadcast floating-point immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE broadcast general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE broadcast general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE broadcast indexed element<V>

Original text: Is a width specifier, encoded in "tsz", where 00000->RESERVED, 10000->Q, x1000->D, xx100->S, xxx10->H and xxxx1->B.

SVE broadcast indexed element<T>

Original text: Is the size specifier, encoded in "tsz", where 00000->RESERVED, 10000->Q, x1000->D, xx100->S, xxx10->H and xxxx1->B.

SVE broadcast integer immediate (unpredicated)<shift>

Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.

SVE broadcast integer immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE broadcast integer immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE broadcast predicate element<T>

Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 1000->D, x100->S, xx10->H and xxx1->B.

SVE compress active elements<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

SVE conditionally broadcast element to vector<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE conditionally extract element to SIMD&FP scalar<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE conditionally extract element to SIMD&FP scalar<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE conditionally extract element to general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE conditionally extract element to general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE conditionally terminate scalars<R>

Original text: Is a width specifier, encoded in "sz", where 0->W and 1->X.

SVE constructive prefix (predicated)<ZM>

Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.

SVE constructive prefix (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE contiguous prefetch (scalar plus immediate)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE contiguous prefetch (scalar plus scalar)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

SVE contiguous store (scalar plus immediate)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE contiguous store (scalar plus immediate)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE contiguous store (scalar plus immediate)<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SVE contiguous store (scalar plus scalar)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE contiguous store (scalar plus scalar)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE contiguous store (scalar plus scalar)<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

SVE copy SIMD&FP scalar register to vector (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE copy SIMD&FP scalar register to vector (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE copy floating-point immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE copy general register to vector (predicated)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE copy general register to vector (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE copy integer immediate (predicated)<shift>

Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.

SVE copy integer immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE copy integer immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

SVE extract element to SIMD&FP scalar register<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE extract element to SIMD&FP scalar register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE extract element to general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE extract element to general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE extract mask predicate from predicate-as-counter<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE floating-point arithmetic (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point arithmetic (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SVE floating-point arithmetic (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point arithmetic (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SVE floating-point arithmetic with immediate (predicated)<const>

Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.0 and 1->#1.0.

SVE floating-point arithmetic with immediate (predicated)<const>

Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.5 and 1->#1.0.

SVE floating-point arithmetic with immediate (predicated)<const>

Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.5 and 1->#2.0.

SVE floating-point arithmetic with immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point compare vectors<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point compare with zero<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point complex add (predicated)<const>

Original text: Is the const specifier, encoded in the "rot" field, where 0->#90 and 1->#270.

SVE floating-point complex add (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point complex multiply-add (indexed)<const>

Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.

SVE floating-point complex multiply-add (predicated)<const>

Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.

SVE floating-point complex multiply-add (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point convert to integer<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point exponential accelerator<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point multiply-accumulate writing addend<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point multiply-accumulate writing addend<T>

Original text: Is the size specifier, encoded in "size", where 01->H, 10->S and 11->D.

SVE floating-point multiply-accumulate writing multiplicand<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point reciprocal estimate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point recursive reduction<V>

Original text: Is a width specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point recursive reduction<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point recursive reduction (quadwords)<T>

Original text: Is an arrangement specifier, encoded in "size", where 00->RESERVED, 01->8H, 10->4S and 11->2D.

SVE floating-point recursive reduction (quadwords)<Tb>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point round to integral value<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point serial reduction (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point serial reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point trig multiply-add coefficient<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point trig select coefficient<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE floating-point unary operations<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE inc/dec register by element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

SVE inc/dec register by predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE inc/dec vector by element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

SVE inc/dec vector by predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE index generation (immediate start, immediate increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE index generation (immediate start, register increment)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE index generation (immediate start, register increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE index generation (register start, immediate increment)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE index generation (register start, immediate increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE index generation (register start, register increment)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE index generation (register start, register increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE insert SIMD&FP scalar register<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE insert SIMD&FP scalar register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE insert general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

SVE insert general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer add reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer add reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SVE integer add reduction (quadwords)<T>

Original text: Is an arrangement specifier, encoded in "size", where 00->16B, 01->8H, 10->4S and 11->2D.

SVE integer add reduction (quadwords)<Tb>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer add/subtract immediate (unpredicated)<shift>

Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.

SVE integer add/subtract immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer add/subtract vectors (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer add/subtract vectors (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer clamp<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare scalar count and limit<R>

Original text: Is a width specifier, encoded in "sf", where 0->W and 1->X.

SVE integer compare scalar count and limit<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare scalar count and limit (predicate pair)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare scalar count and limit (predicate-as-counter)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare scalar count and limit (predicate-as-counter)<vl>

Original text: Is the vl specifier, encoded in the "vl" field, where 0->VLx2 and 1->VLx4.

SVE integer compare vectors<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare vectors<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SVE integer compare with signed immediate<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare with unsigned immediate<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer compare with wide elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

SVE integer divide vectors (predicated)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

SVE integer dot product (unpredicated)<Tb>

Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.

SVE integer dot product (unpredicated)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

SVE integer min/max immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer min/max reduction (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer min/max reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer min/max reduction (quadwords)<T>

Original text: Is an arrangement specifier, encoded in "size", where 00->16B, 01->8H, 10->4S and 11->2D.

SVE integer min/max reduction (quadwords)<Tb>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer min/max/difference (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer multiply immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer multiply vectors (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer multiply-accumulate writing addend (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer multiply-add writing multiplicand (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE integer unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

SVE integer unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

SVE partition break condition<ZM>

Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.

SVE permute predicate elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE permute vector elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE permute vector elements (quadwords)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE pointer conflict compare<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE predicate count (predicate-as-counter)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

SVE predicate count (predicate-as-counter)<vl>

Original text: Is the vl specifier, encoded in the "vl" field, where 0->VLx2 and 1->VLx4.

SVE predicate initialize<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.