SM3PARTW2

SM3PARTW2 takes three 128-bit vectors from three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive-OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information.

Advanced SIMD
(FEAT_SM3)

313029282726252423222120191817161514131211109876543210
11001110011Rm110001RnRd
Oopcode

SM3PARTW2 <Vd>.4S, <Vn>.4S, <Vm>.4S

if !IsFeatureImplemented(FEAT_SM3) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m, 128]; bits(128) Vn = V[n, 128]; bits(128) Vd = V[d, 128]; bits(128) result; bits(128) tmp; bits(32) tmp2; tmp<127:0> = Vn EOR (ROL(Vm<127:96>, 7):ROL(Vm<95:64>, 7):ROL(Vm<63:32>, 7):ROL(Vm<31:0>, 7)); result<127:0> = Vd<127:0> EOR tmp<127:0>; tmp2 = ROL(tmp<31:0>, 15); tmp2 = tmp2 EOR ROL(tmp2, 15) EOR ROL(tmp2, 23); result<127:96> = result<127:96> EOR tmp2; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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