SM3TT1A

SM3TT1A takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a three-way exclusive-OR of the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values:

The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 9.

Advanced SIMD
(FEAT_SM3)

313029282726252423222120191817161514131211109876543210
11001110010Rm10imm200RnRd
opcode

SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]

if !IsFeatureImplemented(FEAT_SM3) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer i = UInt(imm2);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

<imm2>

Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m, 128]; bits(128) Vn = V[n, 128]; bits(128) Vd = V[d, 128]; bits(32) WjPrime; bits(128) result; bits(32) TT1; bits(32) SS2; WjPrime = Elem[Vm, i, 32]; SS2 = Vn<127:96> EOR ROL(Vd<127:96>, 12); TT1 = Vd<63:32> EOR (Vd<127:96> EOR Vd<95:64>); TT1 = (TT1+Vd<31:0>+SS2+WjPrime)<31:0>; result<31:0> = Vd<63:32>; result<63:32> = ROL(Vd<95:64>, 9); result<95:64> = Vd<127:96>; result<127:96> = TT1; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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