SMLALL (multiple and indexed vector)

Multi-vector signed integer multiply-add long-long by indexed element

This signed integer multiply-add long-long instruction multiplies each signed 8-bit or 16-bit element in the one, two, or four first source vectors with each signed 8-bit or 16-bit indexed element of second source vector, widens each product to 32-bits or 64-bits and destructively adds these values to the corresponding 32-bit or 64-bit elements of the ZA quad-vector groups.

The elements within the second source vector are specified using an immediate element index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 3 to 4 bits depending on the size of the element.

The quad-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.

It has encodings from 6 classes: One ZA quad-vector of 32-bit elements , One ZA quad-vector of 64-bit elements , Two ZA quad-vectors of 32-bit elements , Two ZA quad-vectors of 64-bit elements , Four ZA quad-vectors of 32-bit elements and Four ZA quad-vectors of 64-bit elements

One ZA quad-vector of 32-bit elements
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 32; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn); constant integer m = UInt('0':Zm); constant integer offset = UInt(off2:'00'); constant integer index = UInt(i4h:i4l); constant integer nreg = 1;

One ZA quad-vector of 64-bit elements
(FEAT_SME_I16I64)

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then UNDEFINED; constant integer esize = 64; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn); constant integer m = UInt('0':Zm); constant integer offset = UInt(off2:'00'); constant integer index = UInt(i3h:i3l); constant integer nreg = 1;

Two ZA quad-vectors of 32-bit elements
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 32; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'0'); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer index = UInt(i4h:i4l); constant integer nreg = 2;

Two ZA quad-vectors of 64-bit elements
(FEAT_SME_I16I64)

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then UNDEFINED; constant integer esize = 64; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'0'); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer index = UInt(i3h:i3l); constant integer nreg = 2;

Four ZA quad-vectors of 32-bit elements
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 32; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'00'); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer index = UInt(i4h:i4l); constant integer nreg = 4;

Four ZA quad-vectors of 64-bit elements
(FEAT_SME_I16I64)

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then UNDEFINED; constant integer esize = 64; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'00'); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer index = UInt(i3h:i3l); constant integer nreg = 4;