SMLALL (multiple vectors)

Multi-vector signed integer multiply-add long-long

This signed integer multiply-add long-long instruction multiplies each signed 8-bit or 16-bit element in the two or four first source vectors with each signed 8-bit or 16-bit element in the one, two, or four second source vectors, widens each product to 32-bits or 64-bits and destructively adds these values to the corresponding 32-bit or 64-bit elements of the ZA quad-vector groups.

The quad-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo half or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.

It has encodings from 2 classes: Two ZA quad-vectors and Four ZA quad-vectors

Two ZA quad-vectors
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'0'); constant integer m = UInt(Zm:'0'); constant integer offset = UInt(o1:'00'); constant integer nreg = 2;

Four ZA quad-vectors
(FEAT_SME2)

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'00'); constant integer m = UInt(Zm:'00'); constant integer offset = UInt(o1:'00'); constant integer nreg = 4;