SQDECD (vector)

Signed saturating decrement vector by multiple of 64-bit predicate constraint element count

Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The results are saturated to the 64-bit signed integer range.

The named predicate constraint limits the number of active elements in a single predicate to:

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

313029282726252423222120191817161514131211109876543210
000001001110imm4110010patternZdn
size<1>size<0>DU

SQDECD <Zdn>.D{, <pattern>{, MUL #<imm>}}

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer dn = UInt(Zdn); constant bits(5) pat = pattern; constant integer imm = UInt(imm4) + 1; constant boolean unsigned = FALSE;

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<pattern>

Is the optional pattern specifier, defaulting to ALL, encoded in pattern:

pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL
<imm>

Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer count = DecodePredCount(pat, esize); constant bits(VL) operand1 = Z[dn, VL]; bits(VL) result; for e = 0 to elements-1 constant integer element1 = Int(Elem[operand1, e, esize], unsigned); (Elem[result, e, esize], -) = SatQ(element1 - (count * imm), esize, unsigned); Z[dn, VL] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.