SQSHL (immediate)

Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = esize; integer elements = 1; integer shift = UInt(immh:immb) - esize; boolean src_unsigned; boolean dst_unsigned; case op:U of when '00' UNDEFINED; when '01' src_unsigned = FALSE; dst_unsigned = TRUE; when '10' src_unsigned = FALSE; dst_unsigned = FALSE; when '11' src_unsigned = TRUE; dst_unsigned = TRUE;

Vector

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; integer shift = UInt(immh:immb) - esize; boolean src_unsigned; boolean dst_unsigned; case op:U of when '00' UNDEFINED; when '01' src_unsigned = FALSE; dst_unsigned = TRUE; when '10' src_unsigned = FALSE; dst_unsigned = FALSE; when '11' src_unsigned = TRUE; dst_unsigned = TRUE;