SQSHRN, SQSHRN2

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.

If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
010111110!= 0000immb100101RnRd
Uimmhop

SQSHRN <Vb><d>, <Va><n>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then UNDEFINED; if immh<3> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = esize; integer elements = 1; integer part = 0; integer shift = (2 * esize) - UInt(immh:immb); boolean round = (op == '1'); boolean unsigned = (U == '1');

Vector

313029282726252423222120191817161514131211109876543210
0Q0011110!= 0000immb100101RnRd
Uimmhop

SQSHRN{2} <Vd>.<Tb>, <Vn>.<Ta>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; integer shift = (2 * esize) - UInt(immh:immb); boolean round = (op == '1'); boolean unsigned = (U == '1');

Assembler Symbols

<Vb>

Is the destination width specifier, encoded in immh:

immh <Vb>
0001 B
001x H
01xx S
1xxx RESERVED
<d>

Is the number of the SIMD&FP destination register, in the "Rd" field.

<Va>

Is the source width specifier, encoded in immh:

immh <Va>
0001 H
001x S
01xx D
1xxx RESERVED
<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the scalar variant: is the right shift amount, in the range 1 to the destination operand width in bits, encoded in immh:immb:

immh <shift>
0001 16 - UInt(immh:immb)
001x 32 - UInt(immh:immb)
01xx 64 - UInt(immh:immb)
1xxx RESERVED

For the vector variant: is the right shift amount, in the range 1 to the destination element width in bits, encoded in immh:immb:

immh <shift>
0001 16 - UInt(immh:immb)
001x 32 - UInt(immh:immb)
01xx 64 - UInt(immh:immb)
1xxx RESERVED
2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:

Q 2
0 [absent]
1 [present]
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Tb>

Is an arrangement specifier, encoded in immh:Q:

immh Q <Tb>
0001 0 8B
0001 1 16B
001x 0 4H
001x 1 8H
01xx 0 2S
01xx 1 4S
1xxx x RESERVED
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ta>

Is an arrangement specifier, encoded in immh:

immh <Ta>
0001 8H
001x 4S
01xx 2D
1xxx RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n, datasize*2]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = RShr(Int(Elem[operand, e, 2*esize], unsigned), shift, round); (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part, datasize] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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