SRSHR

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
0101111101xxximmb001001RnRd
Uimmho1o0

SRSHR D<d>, D<n>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; constant integer esize = 8 << 3; constant integer datasize = esize; integer elements = 1; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');

Vector

313029282726252423222120191817161514131211109876543210
0Q0011110!= 0000immb001001RnRd
Uimmho1o0

SRSHR <Vd>.<T>, <Vn>.<T>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the scalar variant: is the right shift amount, in the range 1 to 64, encoded as 128 - UInt("immh:immb").

For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded in immh:immb:

immh <shift>
0001 16 - UInt(immh:immb)
001x 32 - UInt(immh:immb)
01xx 64 - UInt(immh:immb)
1xxx 128 - UInt(immh:immb)
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in immh:Q:

immh Q <T>
0001 0 8B
0001 1 16B
001x 0 4H
001x 1 8H
01xx 0 2S
01xx 1 4S
1xxx 0 RESERVED
1xxx 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) operand2; bits(datasize) result; integer element; operand2 = if accumulate then V[d, datasize] else Zeros(datasize); for e = 0 to elements-1 element = RShr(Int(Elem[operand, e, esize], unsigned), shift, round); Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d, datasize] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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