ST1W (scalar plus scalar, single register)

Contiguous store words from vector (scalar index)

Contiguous store of words from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 4 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.

It has encodings from 2 classes: SVE and SVE2

SVE

313029282726252423222120191817161514131211109876543210
1110010101szRm010PgRnZt

ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if Rm == '11111' then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 32 << UInt(sz); constant integer msize = 32;

SVE2
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
11100101000Rm010PgRnZt

ST1W { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

if !IsFeatureImplemented(FEAT_SVE2p1) then UNDEFINED; if Rm == '11111' then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 128; constant integer msize = 32;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<T>

Is the size specifier, encoded in sz:

sz <T>
0 S
1 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(64) offset; bits(64) addr; bits(VL) src; constant integer mbytes = msize DIV 8; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); src = Z[t, VL]; base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>; addr = AddressIncrement(addr, mbytes, accdesc);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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