STLR

Store-Release Register stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.

It has encodings from 2 classes: No offset and Pre-index

No offset

313029282726252423222120191817161514131211109876543210
1x001000100(1)(1)(1)(1)(1)1(1)(1)(1)(1)(1)RnRt
sizeLRso0Rt2

32-bit (size == 10)

STLR <Wt>, [<Xn|SP>{, #0}]

64-bit (size == 11)

STLR <Xt>, [<Xn|SP>{, #0}]

integer t = UInt(Rt); integer n = UInt(Rn); boolean wback = FALSE; integer offset = 0; boolean rt_unknown = FALSE; constant integer elsize = 8 << UInt(size); constant integer datasize = elsize; boolean tagchecked = n != 31;

Pre-index
(FEAT_LRCPC3)

313029282726252423222120191817161514131211109876543210
1x01100110000000000010RnRt
sizeL

32-bit (size == 10)

STLR <Wt>, [<Xn|SP>, #-4]!

64-bit (size == 11)

STLR <Xt>, [<Xn|SP>, #-8]!

boolean wback = TRUE; integer t = UInt(Rt); integer n = UInt(Rn); constant integer datasize = 8 << UInt(size); integer offset = -1 * (1 << UInt(size)); boolean tagchecked = TRUE; boolean rt_unknown = FALSE; if n == t && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

Operation

bits(64) address; constant integer dbytes = datasize DIV 8; AccessDescriptor accdesc = CreateAccDescAcqRel(MemOp_STORE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); bits(datasize) data; if rt_unknown then data = bits(datasize) UNKNOWN; else data = X[t, datasize]; Mem[address, dbytes, accdesc] = data; if wback then if n == 31 then SP[] = address; else X[n, 64] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.