Store Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about addressing modes, see Load/Store addressing modes. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| x | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | imm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
// Empty.
| <Wt1> |
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Wt2> |
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); if opc<0> == '1' then UNDEFINED; integer scale = 2 + UInt(opc<1>); constant integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale); boolean tagchecked = n != 31;
bits(64) address; bits(64) address2; bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, TRUE, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); data1 = X[t, datasize]; data2 = X[t2, datasize]; address2 = AddressIncrement(address, dbytes, accdesc); Mem[address, dbytes, accdesc] = data1; Mem[address2, dbytes, accdesc] = data2;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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